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Verilog HDL operators can be divided into several groups. The arithmetic operators can be used with all data types. The modulus operator is not allowed for real data type variables. For the modulus operator, the result takes the sign of the first operand. Examples of using these operators are shown in Example 1.
The relational operators are used to compare expressions. The value returned by the relational operators is 0 if the expression evaluates to false and 1 if expression evaluates to true.
Examples of using the relational operators are shown in Example 2. The equality operators are used to compare expressions. If a comparison fails, then the result will be 0, otherwise it will be 1. Otherwise it will be true or false. Examples of using the equality operators are shown in Example 3. The logical operators are used to connect expressions.
The result for these operators is 0 when false , 1 when true , and unknown x - when ambiguous. Examples of using the logical operators are shown in Example 4. The bit-wise operators calculate each bit of results by evaluating the logical expression on a pair of corresponding operand bits. Examples of using the bit-wise operators are shown in Example 5. The reduction operator produces a 1-bit result.
This result is calculated by recursively applying bit-wise operation on all bits of the operand. At each step of this recursive calculation the logical bit-wise operation is performed on the result of a previous operation and on the next bit of the operand.
The operation is repeated for all bits of the operand. Examples of using the reduction operators are in shown Example 6. The shift operators perform left and right shifts on their left operand by the number of positions specified by their right operand.
All vacated bits are filled with zeroes. If the expression that specifies the number of bits to shift right operand has unknown x or high-impedance z value, then result will be unknown. Examples of using the shift operators are in shown Example 7.